After the layout is signed off, the tapeout should be done on the foundry. Tapeout usually includes creation ofphotomasks for particular lithographic fabrication technology and production of an “engineering” wafer lot. Our mask designers have experience across a wide range of technology nodes from 180 nm down to 5 nm, including most advanced FinFET nodes of leading semiconductor foundries.

They do all stages of sign-off process and ensure 100% match with the technology process requirements.We perform all required interaction with the foundry and control the schedule & quality of tapeout process.

After accomplishing the lithography process, silicon wafers are usually cut to separate silicon dies and packaged according to ASIC desired packaging type.We help customers in designing proper package and take in our hands interaction with package manufacturers and assembly faculities, perform logistics of wafers from the foundry to the assembly stage and ship ASIC engineering samples to the customer.