Engineering samples of the ASIC are subject to extensive inspection and characterization during bring up process of powering and testing. Usually, this process results in forming two documents:
characterization data — how well the part performs compared to specification,
errata — list of any unexpected behavior encountered during the testing.
We can perform characterization and testing for ASICs as a whole, and for particular function blocks, including but not limited to:
physical IP blocks like SERDES, analog-to-digital (ADC) and digital-to-analog converters (DAC),phase-locked loops (PLL),etc.
logical IP blocks like CPU cores, accelerators, controllers, on-the-chip networks
power distribution circuits, clock trees, etc.
For certain customers we develop test boardsthat help us to fully characterize ASIC behavior across all process, voltage and temperature corner cases, using both predetermined and random input values. Alternatively, we provision wafer-level probing, which has an advantage of accumulating large amounts of data in a shorter time frame, as well as more accurate results thanks to elimination of packaging parasitic effects.
During IC development we apply designfor testing (DFT) techniques. This approach makesit possible to carry out thorough examination against the intended reference, as well as helps to locate issues. Depending on the nature of discovered issues, we may develop either hardware (silicon) fix or software workarounds — in accordance with your policy on non-recurring engineering (NRE) spending and expected production volumes.