Physical design of integrated circuits results increating the topology (layout) of ASIC. It begins with synthesis, during which RTL description is converted into a network-like list of logic gates. Usually, these gates are presented by the standard cells provided by the foundry, but full custom design is also an option. After partitioning the list into functional blocks and doing an overall floor planning, gates are placed on the ASIC floor plan so that their locations don’t overlap. To meet performance and power constraints, multiple cycles of placement are typically preformed. Then clock signal trees are added, routing connections between the gates is performed, and the whole construct undergoes final optimization for timing, noise reduction and yield increase. Design for manufacturability (DFM) methodology involves further adjustments for efficient production according to the rules of the foundry.

Electronic design automation (EDA) software we use allows for quick layout updates when a change is needed. Since connections are automatically tracked by software, changes in layout do not invalidate layout-versus-schematic (LVS) checking results. Final verification that we perform consists of formal equivalence checking against RTL behaviorand design rule checking (DRC) against DFM rules, such as width, spacing and closure of elements.